The present invention relates to a method of manufacturing semiconductor devices and more specifically to a method of manufacturing a high-performance metal oxide semiconductor field-effect transistor (MOSFET) with small resistance of gate electrode and PN junction capacitance.
Dynamic random access memories (DRAMs), a typical example of semiconductor integrated circuit device using silicon, are currently mass-produced as 4-Mbit products using the 0.8 micron manufacturing technology. 16-Mbit products have also started to be mass-produced using the next-generation 0.5 micron manufacturing technology. With advances of micro-fabrication technologies, the semiconductor devices tend to become smaller and smaller in size.
In the MOSFETs with channel length of less than half-micron, however, the velocity of electrons or holes flowing through a channel region are near a saturation speed. Hence, a further reduction in the channel length is not expected to result in a current becoming large in reverse proportion to the channel length.
Another drawback is that as the micro-fabrication advances, the impurity concentration in the substrate increases. As a result of high electric field caused by the impurity concentration, mobility of electrons and holes becomes lower because of the scattering at Si(a substrate)/SiO2(a gate oxide formed on the substrate) interface. This is another factor that reduces the merit of increased current realized by micro-fabrication.
Further, an increase in impurity concentration in the substrate leads to an increase in the PN junction capacitance because the width of the depletion layer is narrowed. The finer gate electrode causes an increase in the gate resistance. These combine to prevent performance improvement that would otherwise be realized by the micro-fabrication of MOSFET. These are explained in more detail by referring to FIG. 4.
Reference numeral 1 represents a semiconductor substrate; 2 a device isolation oxide film; 100, 100' polysilicon gate electrodes; 11 a silicon dioxide film; 12, 12' lightly doped impurity layers; 13, 13' sidewall insulation films; 14, 14' highly doped impurity layers; 15, 15' silicide, films; 16 an interlayer insulation film; 17 a metal plug; 18 a metal interconnect; 21, 22 lightly doped impurity layers; 41, 42 impurity layers; and 91, 92 punch-through stoppers.
FIG. 4 shows a cross section of a semiconductor device. Here, let us take an example of a complementary MOS (CMOS) in which MOSFETs with different conductivity types exist on the same substrate.
A characteristic configuration of MOSFETs with the channel length of less than half-micron includes punch-through stoppers 91, 92 to prevent a punch-through between source and drain, silicide films 15, 15' to reduce resistance of electrodes, and polysilicon gate electrodes 100, 100' with different conductivity types.
When the lightly doped impurity layer 21 has a p-type conductivity, the punch-through stopper 92 has the same p-type conductivity as the lightly doped impurity layer 21 and has a higher impurity concentration. The punch-through stopper 91 and the lightly doped impurity layer 22 are of n type and the impurity concentration of the punch-through stopper 91 is higher than that of the lightly doped impurity layer 22.
The punch-through stopper 91 prevents the depletion layer in the lightly doped impurity layer 22 at the PN junction between the source(or the drain) of the first MOSFET (highly doped impurity layer 14) and the lightly doped impurity layer 22 from protruding into the channel region (so-called short channel effect). This lowers the leakage current between the source and the drain of the first MOSFET. The punch-through stopper 92 prevents the depletion layer in the lightly doped impurity layer 21 at the PN junction between the source (or the drain) of the second MOSFET (highly doped impurity layer 14') and the lightly doped impurity layer 21 from protruding into the channel region. This lowers the leakage current between the source and drain in the second MOSFET.
The silicide films 15, 15' on the highly doped impurity layers 14, 14' and the polysilicon gate electrodes 100, 100' have a function of reducing the resistance of these conductive layers. The above-mentioned highly doped impurity layer becomes thin as the MOSFET becomes fine and its resistance increases to that extent if it has the same impurity concentration. So far the resistance of the highly doped impurity layer is sufficiently small when compared with the channel resistance and thus does not directly affect the current of the MOSFET. Although the channel resistance decreases with the reduction in the channel length, the resistance of the highly doped impurity layer increases to become equal to that of the channel resistance. As a result, the voltage drop in the highly doped impurity layer is seen remarkable, making it impossible to derive the expected performance of the MOSFET. As a means to prevent this and to reduce the resistance, a silicide film may be used. By using salicide (self-aligned silicide) technology, the silicide film can be formed on both the polysilicon gate electrodes 100, 100' and the highly doped impurity layers 12, 12' (source and drain).
The first MOSFET and the second MOSFET have gate electrodes of different conductivity types. The reason that different conductivity types are used is to make both the N-channel MOSFET (second MOSFET) and the P-channel MOSFET a surface channel type. The P-channel MOSFET, like the N-channel MOSFET, has so far used a polysilicon containing a high concentration of n-type impurity for the gate electrode. In the P-channel MOSFET, however, because its work function difference from that of the substrate is small, the gate voltage (threshold voltage) to turn on the MOSFET becomes high. Thus, the channel region is doped with an impurity (boron) of a conduction type different from that of the substrate to make areas close to the surface a P type and thereby to adjust the threshold voltage. In such an impurity distribution, holes flow inside the substrate. Thus, such an MOSFET is called a buried channel type.
Because the buried channel type MOSFET has its channel region apart from the interface between the substrate and a gate oxide film formed under the gate electrode, the holes are hardly distracted by the gate oxide film surface and the mobility of the holes therefore is little lowered. The separation of the channel region from the interface, however, makes more likely an interference with the depletion layer between the source and the drain, resulting in a leakage current. This problem can be solved by forming the gate electrode of the P-channel MOSFET With a P-channel polysilicon film to make the P-channel MOSFET as the surface channel type, as in the N-channel MOSFET.
A variety of improvements have been made in this way for realizing finer fabrication of MOSFETs and for higher performances. The measures taken for improvements that were mentioned above have also drawbacks of preventing performance improvement and rendering the manufacturing process more difficult.
For example, the punch-through stoppers 91, 92 to limit the leakage current caused by the short channel effect increase the concentration of impurity in the channel region, and therefore reduce the mobility of electrons and holes, which in turn leads to reduction in the channel current. Further, because the depletion layer is thin, the PN junction capacitance increases prolonging the signal delay time. This problem has been dealt with so far by reducing the size and increasing the channel current. When the channel length is in the order of half-micron, however, the velocity of electrons and holes becomes saturated and a further reduction in the channel length does not necessarily result in an increased channel current. It is found therefore that the reduction in the channel length alone cannot cope with the reduction in the mobility and the increase in the junction capacitance and that the performance of the MOSFETs and the CMOSs using such MOSFETs deteriorate.
If the polysilicon gate electrodes 100, 100' are used in which silicide is grown near the surface, the resistance also increases as the device size is reduced. This is because as the size of the gate electrode decreases, the reaction between polysilicon and metal becomes uneven. Even with the highly doped impurity layer (source and drain) with a far larger area than the gate electrode, there is also a limit in another sense to siliciding. This is because as the highly doped impurity layer becomes thin, it is impossible to form a sufficiently thick silicide layer. Further, because the silicide films 15, 15' are formed inside the semiconductor substrate, regions containing impurities at high concentrations are silicided. Hence, the remaining junction regions become relatively low concentration areas, which are not preferable for reducing the resistance of the highly doped impurity layer.
In addition to reducing resistance, CMOSs have requirements that polysilicons of different conductivity types be used as practically as possible for gate electrodes. This brings an increase in the number of steps in the gate electrode forming process, causing problems of an increased LSI cost and a lowered yield.